Circuit arrangement for generating synchronization signals in a transmission of data

ABSTRACT

In a transmission of data upon employment of binarily coded data signals (D), reception clocks (ET) with which the data signals (D) are sampled in their middles are generated for the recovery of the transmitted data. The reception clocks (ET) are thereby synchronized phase-wise by the synchronization signals (SY) generated from the data signals (D). In order to also be able to sample the data signals (D) in their middles insofar as possible given distortions of the data signals (D) up to 50%, the synchronization signals (SY) are inventively generated taking the respective distortion into consideration. To this end, a counter (Z) is provided that is respectively counted from an initial value up to a final value by high-frequency clock pulses (T3). Given changes of the binary value of the data signals (D), a synchronization unit (SYS) sets the counter (Z) to its initial value. The counter (Z) is preceded by a switch unit (SS) that always through-connects clock pulses (T1) having a higher repetition rate whenever the counter (Z) has not yet reached its final value at the end of a data signal (D). An output unit (AS) always outputs a synchronization signal (SY) when the counter (Z) reaches its final value. The invention can be particularly employed in a transmission of data wherein the reception clocks allocated to the data signals are generated at the receiver side.

BACKGROUND OF THE INVENTION

The invention is directed to a circuit arrangement for generatingsynchronization signals in a transmission of data from a transmissionunit to a reception unit, whereby the data are transmitted by binarilycoded data signals that are sampled by reception clocks for the recoveryof the transmitted data and whereby the reception clocks aresynchronized phase-wise by synchronization signals allocated to the datasignals upon employment of a counter that is respectively counted froman initial value up to a final value by clock pulses whose repetitionrate is significantly higher than the repetition rates of the datasignals.

It is notoriously known to transmit data with binary data signals from atransmission unit to a reception unit without accompanying clock pulses.In such a transmission, a clock control is provided in the receptionunit, this clock control generating reception clocks from the receiveddata signals and supplying them to a sampling unit. The reception clockstherein sample the data signals and recover the transmitted data fromthe data signals. To this end, the data signals should be respectivelysampled in their middle insofar as possible.

Such a reception unit of the prior art is shown in FIG. 1 in the form ofa block circuit diagram and its functioning shall be explained ingreater detail together with the time diagrams shown in FIG. 2, the timet being shown therein in abscissa direction and the momentary values ofsignals being shown therein in ordinate direction.

Given the reception unit shown as a block circuit diagram in FIG. 1, thebinarily coded data signals D are supplied, first, to a pulse generatorIG and, second, to the sampling unit AB that recovers the transmitteddata from the data signals D upon employment of reception clock ET andmakes them available for a further processing as received data ED. Thereception clock ET is generated in a clock control TS. For synchronizingthe reception clock ET with the data signals D, the pulse generator IGgenerates synchronization signals SY. These synchronization signals SYare adjacent at the clock control TS and the latter sets the phaserelation of the reception clock ET such that the reception clock ETalways samples the data signals D in its middles insofar as possible.

The data signals D shown in FIG. 2 are undistorted data signals, i.e.they change their binary values at whole multiples of prescribed timeintervals. At points in time at the trailing edges of the data signals Dthat respectively correspond to one another, the pulse generator IGgenerates the synchronization signals SY with which the phase relationof the reception clock ET generated in the clock control TS is set suchthat the data signals D are sampled in its middles at times t1 throught5 by the leading edges of the reception clock ET in order to recoverthe received data ED.

The data signals can be subject to distortions in the transmission ofthe data, for example via a radio link affected with interference. Whenthe reception clocks are derived from these data signals, the datasignals cannot be reliably sampled since the reception clocks are onlysynchronized by the edges of the data signals.

SUMMARY OF THE INVENTION

It is therefore the object of the invention to specify a circuitarrangement for generating synchronization signals, the data signalsalso being sampled with great reliability given the employment thereofeven when they are subject to distortions.

In a circuit arrangement of the species initially cited, this object isinventively achieved by the circuit arrangement wherein: the counter canbe respectively counted from a constant initial value up to a constantfinal value; a synchronization unit is provided at which the datasignals are received generating a load signal given every change of thebinary value of the data signals from a first binary value to a secondbinary value, the load signal setting the counter to its initial valueand generating switch-over signals at every change of the binary valuesof the data signals; the counter is preceded by a switch unit at whichthe switch-over signals are received, said switch unit alwaysthrough-connecting first clock pulses having a higher repetition rate tothe counter when a data signal has the first binary value and alwaysthrough-connecting second clock pulses having a lower repetition rate tothe counter whenever a data signal has the second binary value; and anoutput unit is provided that always outputs a synchronization signalwhen the counter has reached its final value.

A particular feature of the invention is comprised therein that thedistortions of the data signals are taken into consideration in thegeneration of the synchronization signals.

The invention makes it possible to also reliably sample data signalshaving distortions of up to 50% of their pulse duration; the circuitarrangement nonetheless requires only little outlay and can bemanufactured as an integrated circuit.

Advantageous developments of the invention include the following. Theswitch unit inhibits the counter after the appearance of everysynchronization signal. The repetition rate of the first clock pulses istwice as high as the repetition rate of the second clock pulses. Thesynchronization unit generates an enable signal and outputs it to theoutput unit and only enables the output of the synchronization signalsthere when the data signal has the first binary value. An enable unit isprovided that outputs an enable signal to the synchronization unit whena prescribed counter reading of the counter that is lower than the finalvalue is reached, the enable signal enabling the generation of asynchronization signal. The enable unit contains a flip-flop that is setby a counter signal allocated to the prescribed counter reading and isreset by the load signal and at whose inverting output the enable signalis output. An inhibit unit is provided that outputs an inhibit signal tothe synchronization unit when the counter transgresses a prescribedcounter reading, the plurality of the data signals being inverted atsynchronization unit with the inhibit signal and an inhibit signal beinggenerated with which the clock pulses are inhibited in the switch unit.The synchronization unit contains an exclusive-OR element having oneinput that receives the data signals and another input that receives anoutput signal of a flip-flop, this flip-flop being switched into arespectively opposite position by the inhibit signal. Thesynchronization unit contains a flip-flop with which the data signalscan be synchronized with the clock pulses. The counter can berespectively counted down from the prescribed initial value to theprescribed final value. An output signal of the counter supplied to theoutput unit is allocated to an overflow signal of the counter.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several Figures in which like referencenumerals identify like elements, and in which:

FIG. 1 is a block circuit diagram of a reception unit for transmitteddata signals;

FIG. 2 depicts time diagrams of signals given the reception ofundistorted data signals;

FIG. 3 is a block circuit diagram of a circuit arrangement of theinvention;

FIG. 4 depicts time diagrams of signals given a reception of distorteddata signals;

FIG. 5 is a circuit diagram of a circuit arrangement of the invention;and

FIG. 6 depicts time diagrams of signals at various points of the circuitarrangement.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Given the circuit arrangement shown in FIG. 3 that can be employed as apulse generator IG in accord with FIG. 1, a clock generator TG generatesclock pulses T1 and T2. The clock pulses T2 have half the repetitionrate of the clock pulses T1 and are generated from the latter byfrequency division, for example with a flip-flop. The clock pulses T1and T2 are supplied to the various components of the circuitarrangement, whereby only the delivery thereof to a switch unit SS isshown. The repetition rate of the clock pulses T1, for example, is equalto 128 times the nominal repetition rate of the data signals D.

Further details of the circuit arrangement shall be set forth in greaterdetail below in conjunction with the time diagrams shown in FIG. 4,wherein the time t is shown in abscissa direction and the momentaryvalues of signals as well as counter readings ZS of a counter Z areanalogously shown in ordinate direction.

The data signals D pend at a synchronization unit SYS wherein they aresynchronized with the clock pulses T1. When a data signal D assumes thebinary value 1, the synchronization unit SYS generates a load pulse Lthat sets the counter Z to an initial value AN, for example 64, withinitial value signals ANS and resets an enable unit FR and also cancelsan inhibit signal S1 for the switch unit SS via the synchronization unitSYS. The synchronization unit SYS also generates a switch-over signal D3for the data pulses T1 and T2, a data signal that through-connects theclock pulses T2 via the switch unit SS to the counter Z as clock pulsesT3. The clock pulses T3 drive the counter Z and deincrement it down to afinal value EN, for example zero. As soon as it reaches a counterreading 32 that corresponds to half the initial value AN, it outputs asignal Z1 that sets the enable unit FR and initiates it to generate anenable signal FRI since the data signal D then comprises a pulseduration of at least 50% of the rated duration in the undistorted case.Otherwise, the inhibit signal S1 would immediately inhibit the output ofthe clock pulses T3 and the counting would thus be terminated.

When the data signals D are undistorted, the corresponding data signal Dis sampled precisely in its middle at time t1 by the reception clock ETand the counter Z reaches the final value EN having the value zeroexactly when the data signal D changes its binary value from 1 to 0. Inthis case, it outputs a final value signal ES to an output unit AS. Withthe change of the binary value, the synchronization unit SYS alsooutputs an enable signal FR2 to the output unit AS and the lattergenerates a synchronization signal SY that serves the purpose of settingthe phase relation of the reception clock ET. Further, thesynchronization signal SY also results in the generation of the inhibitsignal S1 with which the switch unit SS is inhibited and with which thecounting is terminated. At time t2, the data signal D is again sampledin its middle by a reception clock ET. After the next change in thebinary value of the data signal D, a similar procedure then repeats andthe data signal D is again sampled at time t3.

When the data signal D is distorted and already changes its binary valuefrom 1 to 0 at time t4 before the counter Z has reached its final valueEN, the synchronization unit SYS forwards the data signal D4 to theswitch unit SS as switch-over signal and this switch unit SS nowthrough-connects the clock pulses T1 to the counter Z with the higherrepetition rate, so that this reaches its final value En faster and thesynchronization signal SY is output correspondingly earlier at time t5.The phase relation of the reception clock ET is thus again set, so thatthe corresponding data signal D is sampled closer toward its middle attime t6. Events similar to those between times t2 and t5 then repeatbetween times t6 and t9 and the corresponding data signal D is againsampled closer to its middle at time t7 than would be the case withoutthe switching of the clock pulses T1 and T2.

When a data signal D lasts longer than the rated duration in theundistorted case, the counter Z generates a counting signal. Thiscounting signal Z2 is adjacent at an inhibit unit SP that then generatesan inhibit signal ST with which the switch unit SS is likewise inhibitedby the inhibit signal S1 via the synchronization unit SY. Thesynchronization unit SYS is also inhibited and the polarity of the datasignals D is inverted since these are not allowed to have any ratedduration that is greater than 103%. Events corresponding to those giventhe other changes then repeat given the next change of the binary valueof the data signal D.

Instead of being counted down, the counter Z can also be counted up. Inthis case, for example, the initial value signal ANS always sets it tothe initial value AN of zero and the clock pulses T3 then increment itto a final value EN of 64.

In the illustration of FIG. 4, the data signals D are shortened by up to50% due to distortions. The corresponding, undistorted data signals Dare shown in broken lines. As a consequence of the distorted datasignals D, the synchronization signals SY are not always generated atthe edges thereof but by the counter Z that is respectively counted fromthe prescribed initial value AN to the prescribed final value EN. Thesynchronization signal SY with which the reception clock ET issynchronized is generated every time the final value EN is reached. Atthe end of every data signal D having trailing edges, a switch isundertaken from the clock pulses T2 having low repetition rate to theclock pulses T1 having high repetition rate, so that the final value ENis reached faster and the reception clock ET can be synchronizedleading. At time t4 and t8, a switch is respectively undertaken to theclock pulses T1 having the higher repetition rate and the leadingsynchronization signals SY are generated at times t5 and t9.

The circuit diagram shown in FIG. 5 for the circuit arrangement shall beset forth in greater detail below together with the time diagrams shownin FIG. 6, wherein the time t is shown in abscissa direction and themomentary values of signals as well as the counter readings ZS of thecounter Z are analogously shown in ordinate direction.

A clock generator TG is provided for the circuit diagram shown in FIG. 5of the circuit arrangement, this clock generator TG generating clockpulses T1, T1 and T2, whereby the clock pulses T1 have twice therepetition rate of the clock pulses T2 and the clock pulses T1correspond to the inverted clock pulses T1. The repetition rate of theclock pulses T1, for example, is equal to 128 times the repetition rateof the undistorted data signals D.

At the beginning, the circuit arrangement is reset by a reset signal Rthat is adjacent at the components in the illustrated way and resetsflip-flops F1 through F3, F8 and F9. The data signals D are adjacent atan input of an exclusive-OR element A given the employment whereof thepolarity of the data signals D can be inverted as warranted. Theexclusive-OR element A outputs the data signal D1 at its output, thisdata signal D1 being adjacent at the clock input of the flip-flop F1 atwhose data input the binary value 1 is adjacent. When the binary valueof the data signal D changes, for example, from 0 to 1 at time t1, thebinary value of the data signal D1 at the output of the exclusive-ORelement A likewise changes from 0 to 1 and the flip-flop F1 is set,given the condition that the flip-flop F9 is reset. The output of theflip-flop F1 is connected to the data input of the flip-flop F2 at whoseclock input the clock pulses T1 are adjacent and that, together with theflip-flop F3, serves the purpose of synchronization of the data signalsD or, respectively, D1 with the clock pulses T1 and T1. The flip-flop F2is set with the next clock pulses T1.

The non-inverting output of the flip-flop F2 is connected to an input ofan NOR element N2, to the data input of the flip-flop F3, to the resetinput of a flip-flop F4 and to a first input of an NAND element N1 whosesecond input is connected to the inverting output of the flip-flop F3.Since the flip-flop F3 is reset, the NAND element N1 outputs the loadpulse L having the binary value 0 that, due to the initial value signalsANS having the binary values 1000000, loads the value 64 into thecounter Z and resets a flip-flop F5 via an inverter I. The enable signalFR1 at the inverting output of the flip-flop F5 enables an AND elementU2.

The inverting output of the flip-flop F2 is connected to the data inputof the flip-flop F4 at whose clock input the clock pulses T1 areadjacent. The flip-flop F4 has already been reset, so that no change inthe status of the flip-flop F4 ensues with the next clock pulse T1.

The clock pulses T1 are adjacent at the clock input of the flip-flop F3and this flip-flop F3 is also set with the next clock pulse T1. The loadpulse L thus again assumes the binary value 1 and it sets a furtherflip-flop F6 that enables two NAND elements N3 and N4 with an inhibitsignal S1. These NAND elements N3 and N4 are respectively connected toan output of the flip-flop F3 and the data signals D3 and D4, on the onehand, are adjacent thereat as switch-over signals and, second, the clockpulses T1 or, respectively, T2 are also adjacent thereat. Since theflip-flop F3 is set, inverted clock pulses T2 are output via the NANDelement N3 and are supplied to the counter Z as clock pulses T3 via anAND element U1. The counter Z thus begins to count down from its initialvalue 64 to its final value.

As soon as the counter Z has reached its counter reading 32 at time t2,it outputs a corresponding counter signal Z1 that is adjacent at thedata input of the flip-flop F5 and sets it. The enable signal FR1 at theinverting output of this flip-flop F5 now inhibits the AND element U2.The flip-flop F5 essentially forms the enable unit FR and it onlyenables the circuit arrangement when the data are respectively longerthan 50% of their rated duration. Otherwise, the AND element U2 wouldgenerate a reset signal that inhibits the switch unit SS.

At time t3, the data signal D again assumes the binary value 0 and thedata signal D1 thus also assumes the binary value 0. The flip-flop F1 isreset via an NOR element N5 at whose first input the data signal D1 isadjacent and whose second input is connected to the inverting output ofthe flip-flop F1 and is also reset via an OR element O1. The flip-flopF2 is also reset with the next clock pulse T1. In a corresponding way,the next clock pulse T1 resets the flip-flop F3. The next clock pulse T1sets the flip-flop F4 and this in turn holds the flip-flop F5 in the setcondition on the basis of a set signal SE.

The NAND element N3 is inhibited and the NAND element N4 is enabled withthe resetting of the flip-flop F3. Due to the data signal D4, this nowthrough-connects the clock pulses T1 having twice the frequency to thecounter Z, so that this reaches its final value 0 faster.

As soon as the counter Z has reached its final value 0, it outputs anoverflow signal having the binary value 0 as final value signal ES atits output at time t4, this overflow signal setting a flip-flop F7 viathe NOR element N2. The flip-flop F7 outputs the synchronization SY atits output.

Via an OR element O2, the synchronization signal SY resets the flip-flopF6 that in turn inhibits the NAND elements N3 and N4 with the inhibitsignal S1 and prevents a further counting of the counter Z. Theflip-flop F7 is again reset with the next clock pulse T2 and thesynchronization signal SY is thus ended in turn. The synchronizationsignal SY resets the phase of the reception clock ET and the data signalD is again sampled at time t5. An event similar to that following timet1 repeats after time t6. If the binary value of the data signal Dchanges too late and the counter Z has previously reached its finalvalue and outputs the final value ES, the NOR element N2 does not outputa setting signal to the flip-flop F7 since the flip-flop F2 is set andthe NOR element N2 is consequently inhibited.

In case the counter Z has reached a counter reading that is allocated toa distortion of the data signal D by more than 100% before the change ofthe binary value of the data signal D from 1 to 0, it outputs a countersignal Z2 via an AND element U3 to a flip-flop F8 that sets the latterand outputs an inhibit signal S2 at its output. This inhibit signal S2likewise resets the flip-flop F6 and prevents the output of furtherclock pulses T1 or T2 to the counter Z. It also resets the flip-flop F1and sets a flip-flop F9 whose output is connected to the exclusive ORelement A. The exclusive OR element A now inverts the data signal D andan event similar to that between times t1 and t2 repeats with the nextchange of the binary value of the data signal D at time t6.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

What is claimed is:
 1. A circuit arrangement for generatingsynchronization signals in a transmission of data from a transmissionunit to a reception unit, the data being transmitted by binarily codeddata signals that are sampled by reception clocks for the recovery ofthe transmitted data and the reception clocks being phase synchronizedby synchronization signals allocated to the data signals upon employmentof a counter that is respectively counted from an initial value to afinal value by clock pulses whose repetition rate is significantlyhigher than repetition rates of the data signals, comprising: thecounter being respectively counted from a constant initial value to aconstant final value; a synchronization unit receiving the data signals,and generating a load signal given every change of a binary value of thedata signals from a first binary value to a second binary value, saidload signal being received by the counter and setting the counter to itsinitial value, and the synchronization unit also generating switch-oversignals for every change of the binary values of the data signals; thecounter preceded by a switch unit which receives the switch-oversignals, said switch unit always through-connecting first clock pulsesof the reception clocks having a higher repetition rate to the counterwhen a data signal has the first binary value and alwaysthrough-connecting second clock pulses of the reception clocks having alower repetition rate to the counter whenever a data signal has thesecond binary value; and an output unit connected to an output of thecounter that always outputs a synchronization signal when the counterhas reached its final value.
 2. The circuit arrangement according toclaim 1, wherein the switch unit inhibits the counter after theappearance of every synchronization signal.
 3. The circuit arrangementaccording to claim 1, wherein the repetition rate of the first clockpulses is twice as high as the repetition rate of the second clockpulses.
 4. The circuit arrangement according to claim 1, wherein thesynchronization unit generates an enable signal and outputs the enablesignal to the output unit and the output unit thereby only outputtingthe synchronization signals when the data signal has the first binaryvalue.
 5. The circuit arrangement according to claim 1, wherein thecircuit arrangement further comprises an enable unit that outputs anenable signal to the synchronization unit when a prescribed counterreading of the counter that is before than the final value is reached,said enable signal enabling the generation of the synchronizationsignal.
 6. The circuit arrangement according to claim 5, wherein theenable unit contains a flip-flop that is set by a counter signal fromthe counter allocated to the prescribed counter reading and is reset bythe load signal and the enable unit having an inverting output on whichthe enable signal is output.
 7. The circuit arrangement according toclaim 1, wherein the circuit arrangement further comprises an inhibitunit that outputs an external inhibit signal to the synchronization unitwhen the counter transgresses a prescribed counter reading, a pluralityof the data signals being inverted at said synchronization unit withsaid external inhibit signal and an internal inhibit signal generated bysaid synchronization unit with which the clock pulses are inhibited inthe switch unit.
 8. The circuit arrangement according to claim 7,wherein the synchronization unit contains an exclusive-OR element havingone input that receives the data signals and having another input thatreceives an output signal of a flip-flop, the flip-flop being switchedinto a respectively opposite position by the external inhibit signal. 9.The circuit arrangement according to claim 1, wherein thesynchronization unit contains a flip-flop with which the data signalscan be synchronized with the clock pulses.
 10. The circuit arrangementaccording to claim 1, wherein an output signal of the counter suppliedto the output unit is allocated to an overflow signal of the counter.